Phase-locked loops (PLLs) are widely used in timing circuits/blocks associated with data communications, local area networks, processors, and data storage applications to name just a few. A PLL is an electronic circuit that is often employed as a frequency synthesizer in which an oscillator frequency is divided down to a reference frequency that is derived from an accurate source. In PLLs, particularly those used for frequency synthesis in processors, it is often beneficial to detect the loss of an input reference clock as well as the loss of a feedback clock produced by the PLL. Upon detecting loss of a reference clock, it is often desirable to power down the PLL as the circuit may become unstable resulting in an unreliable output clock signal. Similarly, loss of the feedback clock can occur e.g. if the bandwidth of the feedback path is less than the maximum frequency (Fmax) of a voltage-controlled oscillator (VCO) within the PLL. In this case, the PLL typically needs to be reset or pulled out of this state before reliable operation of the PLL can resume.
In the past, detection of reference clock and/or feedback clock signals typically has been performed using analog timers. However, given the reduced headroom and increased leakage often occurring in contemporary logic processes, such analog timers are becoming increasingly difficult to reliably design.